The present invention relates to a semiconductor device and more particularly to a technique which is useful for the I/O cell architecture and layout method of the same.
In this connection, the present inventors examined the semiconductor device technique described below.
Regarding I/O (input/output circuit) areas of an LSI (large-scale integrated circuit), in transmitting signals between areas with different voltages, particularly from an I/O area with a low voltage to an I/O area with a high voltage, it is necessary to shift up the signal level.
Moreover, in this case, layout of the level-up circuit requires high noise sensitivity in wiring for generating signals.
In shifting up the level of a signal through transmission from an I/O area with a low voltage to an I/O area with a high voltage, a true/bar (normal/inverted) signal is generated in a power supply area (area with a low voltage) before shifting up the level. This signal is automatically routed to an I/O area with a high voltage which includes a level shifter circuit, using an ordinary P&R (placement and routing) tool to generate a signal whose level is shifted up.
In this process, in order to reduce the influence of crosstalk noise or the like, pin arrangement must be made so that I/O power supply areas which need level shift-up are close to each other to shorten the length of wiring for true and bar signals.
One example of a technique related to a semiconductor device according to the present invention is a technique described in Japanese Unexamined Patent Publication No.2003-273231. In this technique, shield wires are laid on a boundary of a macro module (analog, etc) inside an LSI core in a way to surround the core area. The shield wires are electrically connected to power wires of another interconnection layer through a power supply terminal or power supply wires of the macro module or the like to fix the electric potential of the shield wires. Then the influence of crosstalk noise or the capacitance generated between wires is estimated to know the accurate value of delay. In the LSI layout process, floorplanning is first done and power wires are arranged (I/O cell layout) before shield wires are formed.